Methods, systems and computer readable media for reconstructing uncorrectable forward error correction (fec) data

ABSTRACT

A method for reconstructing uncorrectable forward error correction (FEC) data includes generating and transcoding a known bit sequence and transmitting a FEC encoded codeword that includes a payload containing the transcoded known bit sequence through a component under test. The method further includes receiving the FEC encoded codeword transmitted via the component under test and determining that the encoded contents of the FEC encoded codeword contains a number of symbol errors that exceeds a predefined threshold. The method also includes utilizing stored scramble seed bits corresponding to an immediately preceding FEC encoded codeword and the transcoded known bit sequence to generate a reconstructed codeword.

TECHNICAL FIELD

The subject matter described herein relates to the detection andprediction of uncorrectable forward error correction (FEC) errors. Moreparticularly, the subject matter described herein relates toreconstructing uncorrectable FEC data.

BACKGROUND

The testing of network equipment can include measuring how accuratelythe equipment can place data on a physical link and send the data toother network equipment over the link. Such measurement is oftenreferred to as a link or component quality measurement, as it measuresthe quality of the physical link and the components used to transmit andreceive data over the link. Examples of link components for which it maybe desirable to evaluate quality include serializer/deserializers(SerDes), retimers, or other components used to place bits on a link orreceive bits from a link.

One way in which link or component quality is measured is by countingthe number of symbol or bit errors that occur over a given amount oftime or per quantity of received data. If no error correcting codes areused on a link, measuring link or component quality based on bit errorsis a relatively simple task. The sending network equipment sends dataover the link, and the receiving network equipment counts the number ofbit errors in the received data as a measurement of link or componentquality.

Error correcting codes, and in particular, forward error correctingcodes, are used by transmitting and receiving network equipment tocorrect bit errors before and/or while the received data is processed bythe receiving network equipment. In some FEC codes, parity symbols orchecksum symbols (e.g., checksums) are inserted in transmitted data, andthe receiving network equipment uses the parity symbols to identify andcorrect symbol errors in the received data, where each symbol is aspecified number of bits. FEC has become essential in high speednetworks, such as 100 gigabit Ethernet networks, to reduce the effectsof symbol or bit errors on transmitted data and to decrease the cost oftransmitting and receiving network equipment. For example, if FEC cancorrect bit errors in received data, lower-cost components can be usedto transmit and receive the data, since the transmission and receptionof the data do not need to be completely free of bit errors.

FEC decoders, such as Reed-Solomon FEC decoders, correct bit errors bycorrecting symbols. Collections of symbols are referred to as codewordsor blocks. A FEC decoder can correct codewords as long as the number ofsymbol errors does not exceed a fixed number of codeword errors in thesymbol. When the number of codeword errors exceeds the threshold, thecodeword is designated as being uncorrectable, as it cannot be correctedby the FEC decoder at the receiver. Uncorrectable codeword errors areundesirable because the underlying data is lost.

In light of these difficulties, there exists a need for improvedmethods, systems, and computer readable media for reconstructinguncorrectable FEC data.

SUMMARY

A method for reconstructing uncorrectable forward error correction (FEC)data is disclosed. The method includes generating and transcoding aknown bit sequence and transmitting a FEC encoded codeword that includesa payload containing the transcoded known bit sequence through acomponent under test. The method further includes receiving the FECencoded codeword transmitted via the component under test anddetermining that the encoded contents of the FEC encoded codewordcontains a number of symbol errors that exceeds a predefined threshold.The method also includes utilizing stored scramble seed bitscorresponding to an immediately preceding FEC encoded codeword and thetranscoded known bit sequence to generate a reconstructed codeword.

In some embodiments of the method, the bit sequence comprises a knownpseudo-random bit sequence.

In some embodiments of the method, transmitting the bit sequence througha component under test comprises transmitting the bit sequence over anEthernet link.

In some embodiments of the method, the stored scramble seed bits and atranscoded data bit are applied to a polynomial associated with a FECdecoder to produce a scrambled bit of the reconstructed codeword.

In some embodiments of the method, the FEC decoder is a Reed-Solomonerror correcting code.

In some embodiments of the method, the reconstructed codeword displaysthe location of symbol errors using lanes marked on a relateduncorrectable codeword.

In some embodiments of the method, the reconstructed codeword isutilized to predict locations of symbol errors in the known bitsequence.

A system for reconstructing uncorrectable forward error correction (FEC)data is also disclosed. The system includes a codeword generatorconfigured for generating and transcoding a known bit sequence andtransmitting a FEC encoded codeword that includes a payload containingthe transcoded known bit sequence through a component under test. Thesystem further includes a codeword analyzer configured for receiving theFEC encoded codeword transmitted via the component under test anddetermining that the encoded contents of the FEC encoded codewordcontains a number of symbol errors that exceeds a predefined threshold.The system further includes a codeword reconstruction engine forutilizing stored scramble seed bits corresponding to an immediatelypreceding FEC encoded codeword and the transcoded known bit sequence togenerate a reconstructed codeword.

In some embodiments of the system, the bit sequence comprises a knownpseudo-random bit sequence.

In some embodiments of the system, the codeword generator is furtherconfigured for transmitting the bit sequence over an Ethernet link.

In some embodiments of the system, the stored scramble seed bits and atranscoded data bit are applied to a polynomial associated with a FECdecoder to produce a scrambled bit of the reconstructed codeword.

In some embodiments of the system, the FEC decoder is a Reed-Solomonerror correcting code.

In some embodiments of the system, the reconstructed codeword displaysthe location of symbol errors using lanes marked on a relateduncorrectable codeword.

In some embodiments of the system, the reconstructed codeword isutilized to predict locations of symbol errors in the known bitsequence.

The subject matter described herein for reconstructing uncorrectable FECdata may be implemented in hardware, software, firmware, or anycombination thereof. As such, the terms “function” or “module” as usedherein refer to hardware, software, and/or firmware for implementing thefeature being described. In one exemplary implementation, the subjectmatter described herein may be implemented using a computer readablemedium having stored thereon computer executable instructions that whenexecuted by the processor of a computer control the computer to performsteps. Exemplary computer readable media suitable for implementing thesubject matter described herein include non-transitory computer-readablemedia, such as disk memory devices, chip memory devices, programmablelogic devices, and application specific integrated circuits. Inaddition, a computer readable medium that implements the subject matterdescribed herein may be located on a single device or computing platformor may be distributed across multiple devices or computing platforms.

BRIEF DESCRIPTION OF THE DRAWINGS

The subject matter described herein will now be explained with referenceto the accompanying drawings, wherein like reference numerals representlike parts, of which:

FIG. 1 is a block diagram of an exemplary test device for reconstructinguncorrectable FEC codewords according to an embodiment of the subjectmatter described herein;

FIG. 2 is a flow diagram of a test device transmission path according toan embodiment of the subject matter described herein;

FIG. 3 is a diagram of a test device receiver path according to anembodiment of the subject matter described herein;

FIG. 4 is a diagram illustrating an exemplary uncorrectable codewodereconstruction path executed by a codeword reconstruction engineaccording to an embodiment of the subject matter described herein; and

FIG. 5 is a flow chart illustrating an exemplary process forreconstructing uncorrectable FEC data.

DETAILED DESCRIPTION

The subject matter described herein includes methods, systems, andcomputer readable media for reconstructing uncorrectable FEC data. FIG.1 is a block diagram of an exemplary system for detecting and remedyinguncorrectable FEC errors. Referring to FIG. 1 , the system includes anetwork equipment test device 100 configured to generate test frame(e.g., an idle packet/frame, a data packet/frame, or any other likepacket/frame) and transmit the test frames to a device under test 102.Device under test 102 may be any suitable network device that includesnetworking capabilities. For example, device under test 102 may be arouter, a switch, a firewall, a network address translator, or similarnetwork component.

In the illustrated example, network equipment test device 100 includes aplurality of port units 104 that transmit test frames (e.g., idlepackets and/or frames) to device under test 102 and receive frames fromdevice under test 102 via physical layer chips 106. Each physical layerchip 106 includes a transmitter for transmitting bit sequences (i.e., inencoded block and/or codeword format) to DUT 102 and a receiver forreceiving bit sequences (i.e., in encoded block and/or codeword format)from DUT 102. In one example, each physical layer chip 106 may beimplemented using an Ethernet transceiver and the links or componentsbeing evaluated for quality include the Ethernet links or components ineach physical layer chip 106 that transmit and receive bits over eachEthernet link. As stated above, examples of such components includesserializer/deserializers, retimers, and other hardware used to transmitand receive encoded blocks or codewords. As described herein, a codewordcomprises a block of scrambled data (e.g., bits or symbols) and anappended checksum symbol (e.g., 30 bit checksum symbol). In someembodiments, the codeword comprise a FEC

In some embodiments, each port unit 104 may be implemented as all orpart of a printed circuit board mounted in a chassis. In the illustratedexample, each port unit 104 includes a bit sequence generator, which inthe illustrated example is a codeword generator 108 (which includes apseudo-random bit sequence (PRBS) generator), memory 110, a codewordanalyzer 112, and a port processor 114. Codeword generator 108 of eachport unit initially generates pseudo-random bit sequences (e.g., testpayloads), which are subsequently organized into blocks and/or codewordsto be transmitted to device under test 102. Physical layer chips 106package the block payloads into frames, transmit the frames to deviceunder test 102, receive frames from device under test 102, and unpackage(e.g., unscramble) the blocks from the received frames in a mannerdescribed below.

Memory 110 stores test configuration information and test results. Portprocessor 114 controls the overall operation of each port unit 104. Inaddition, each port processor 114 may communicate with a controlprocessor 116 over a backplane 118. Control processor 116 may controlthe overall operation of network equipment test device 100. Controlprocessor 116 may also control communications between admin terminal 120and port processors 114. Admin terminal 120 may be a computing devicethrough which a test system operator configures network equipment testdevice 100 and views output generated by network equipment test device100.

In some embodiments, physical layer chips 106 of device under test 102can be configured in loopback mode to loop frames received from testdevice 100 back over the link over which the packets and/or frames arereceived. The physical layer chips 106 receive the looped back framesand provide the bit sequences extracted from the frames to a codewordanalyzer 112. Codeword analyzer 112 is configured for receiving ingressblock and/or codewords and determines whether the same contain anacceptable or unacceptable number of FEC errors (described in greaterdetail below).

The subject matter described herein is not limited to the test setupillustrated in FIG. 1 to reconstructing uncorrectable FEC data. Anysuitable test setup where a block/codeword is transmitted over a link orthrough a component under test and/or a block/codeword is received fromthe link or component under test is intended to be within the scope ofthe subject matter described herein. For example, in FIG. 1 , transmitside components of each physical layer chip 106 in network equipmenttest device 100 or in a network device that is not a network equipmenttest device, such as a switch, a router, or a network card, may beconfigured to loop a bit sequence back to receive side components of thephysical layer chip 106. Codeword analyzers 112 may further include acodeword reconstruction engine (CRE) 122 that is configured to detectthe presence of uncorrectable FEC data in an ingress block/codeword andsubsequently reconstruct the encoded block/codeword as described herein.In some embodiments, codeword reconstruction engine 122 may be embodiedas an algorithm running on a chip-based hardware component or as asoftware component executed by a central processing unit.

In some embodiments, codeword analyzer 112 includes a codeword checker(not shown) that initially receives the ingress blocks/codewords fromlinks or components whose quality is being evaluated. The codewordchecker may also be configured to output the locations of bit and/orsymbol errors in the bit sequence of the received codeword.

In some embodiments, codeword analyzer 112 may determine whether a FECcodeword is uncorrectable by counting the number of symbol errors in theingress block/codeword and determining whether the number of symbolerrors exceeds the uncorrectable threshold for the FEC algorithm beingutilized. Codeword analyzer 112 may be configurable with predefinedthresholds for the number of symbol errors that will result in acodeword being counted as uncorrectable. In Reed-Solomonencoding/decoding, a codeword is divided into N total symbols. The Ntotal symbols include K data symbols of S bits each and N−K checksumsymbols of S bits each. Notably, a Reed-Solomon decoder (e.g., aReed-Solomon error correcting code) can correct up to a total of “T”symbol errors, where T=(N−K)/2. A symbol error is defined as a symbolwith one or more bit errors. Reed-Solomon encoding can correct a symbolif it has only one bit error or up to the symbol size of bit errors. Forexample, a RS(514, 544) decoder with 10 bit symbols (e.g., symbol size“S”=10 bits) means that each codeword contains 544 total codewordsymbols of which 514 symbols are data and 30 symbols are checksumsymbols. As used herein as an example, a RS(514, 544) FEC encoder (onthe transmission port/side) and corresponding decoder (on the receiverport/side) with the following parameters is used:

-   -   N=544, K=514, S=10 bits    -   2T=30, T=15        This means that the decoder can detect up to 15 symbol errors        (“T”) before the codeword will be determined to be        uncorrectable. Accordingly, codeword analyzer 112 may be        configured with the N, K, S, and T parameters for each FEC code        against which the link and/or DUT is being evaluated to        determine the number of uncorrectable errors.

For example, codeword analyzer 112 may count the number of symbol errorsin each codeword and generate corresponding output. In one example,codeword analyzer 112 may compare the number of symbol errors in eachcodeword to the number of symbol errors that would result in anuncorrectable codeword error for each FEC algorithm against which linkor component quality is being evaluated. Codeword analyzer 112 may countand output the number of symbol errors per codeword, the number ofuncorrectable codewords, or other measure of link or component quality.

FIG. 2 illustrates a flow diagram of the operating process 200 ofcodeword generator 108 (as shown in FIG. 1 ). In some embodiments,codeword generator 108 may include, or be a part of, a transmittercomponent of the test device. In some embodiments, process 200 isconducted over a transmit path (e.g., 400GE transmit path) within portunit 104. For example, process 200 is initiated when codeword generator108 generates a raw bitstream input that is to be sent as a transmissionpayload (see step 202). Notably, the raw bitstream can be a PRBS streamthat is generated by a deterministic algorithm associated with codewordgenerator 108 and subsequently divided into symbol blocks. For example,the transmission payload can be segmented into blocks of 544 datasymbols (wherein each data symbol is 10 bits long).

In step 204, the raw bitstream are transcoded into blocks or codewords.For example, codeword generator 108 can process 544 data symbols of theraw bitstream input and compress them to 514 (transcoded) data symbols.

Once transcoding step 204 is executed, codeword generator 108 conducts ascrambling process by applying a transmit scrambler to the payload data(see step 206). Notably, the transcoded block payload is scrambled suchthat a scrambled block payload is produced. The transcoded block payloaddata produced from step 204 may be scrambled using a predefinedpolynomial associated with the transmit scrambler. In some embodiments,the transmit scrambler can be a multiplicative scrambler or any otherscrambler depending on the scrambling mechanism utilized. For example,the predefined polynomial may be a x⁵⁸+x³⁹+1 transmit scrambler.Moreover, the transmit scrambler calculates a new bit (i.e., a“scrambled bit”) based on i) the previous 58 bits and ii) the input bit.The 58 bits are called the “scrambler seed” or “seed bits” for thescrambled output being calculated. Specifically, the transmit scramblercalculates each new scrambled bit by using the preceding 58 bits and the“transcoded” input bit being processed (e.g., using the polynomial).More specifically, the transmit scrambler uses the polynomial togenerate the scrambled payload using an algorithm where each bit of thescrambled payload is created using the previous 58 bits of the scrambledpayload and the input bit. The initial value used before any payloadprocessing is the scrambler seed. Although the following disclosuredescribes the use of 58 seed bits, any number of seed bits (e.g.,largely dependent on the Reed-Solomon FEC coder utilized) can be used bythe transmit scrambler without departing from the scope of the disclosedsubject matter.

Afterwards, lane marker information is added or appended to thescrambled codeword as indicated in step 208. In particular, thescrambled block data produced from step 206 is subsequently overlaidwith FEC lane markers so the receiver port can later identify and/or“lock onto” the boundaries of FEC block and/or codeword. For example, inEthernet transmissions, data can be divided into electrical lanes, whichare multiplexed onto a different number of optical lanes and transmittedover a link. For example, 100 gigabit Ethernet consists of ten 10 Gb/selectrical lanes. 40 gigabit Ethernet consists of four 10 Gb/selectrical lanes. 25 Gb/s Ethernet consists of a single 25 Gb/selectrical lane. The number of bits per lane per time period is referredas the lane width and can be used to establish the aforementioned lanemarkers.

In step 210 of process 200, codeword generator 108 utilizes an FECchecksum calculator to compute appropriate checksum information for thereceived scrambled block output. In some embodiments, the transmit FECchecksum calculator calculates a 30 symbol checksum for every 514-symbolblock of the scrambled block data output.

After the checksum information is calculated, codeword generator 108 canbe configured to append the checksum information to the end of thescrambled block data output to produce an output codeword. Inparticular, along with the calculated symbol checksum, the outputcodeword (i.e., FEC encoded egress codeword) is 544 symbols long.

After the checksum information is combined with the scrambled blockoutput, codeword generator 108 is configured to transmit the resultingcodeword to the device under test as a digital codeword (see step 212).Notably, the resulting FEC encoded egress codeword is transmitted to adevice under test (e.g., DUT 102 in FIG. 1 ) and subsequently forwardedto a receiving port in the test device.

FIG. 3 illustrates a flow diagram of an example operating process 300 ofcodeword analyzer 112. In step 302, codeword analyzer 112 receives ascrambled digital codeword (e.g., FEC encoded egress codeword of 544symbols) from device under test 102 (as shown in FIG. 1 ). In step 304,codeword analyzer 112 may be configured to align the symbols in thereceived codeword in accordance with the lane markers previouslyestablished by codeword generator 108 (e.g., see step 208 in FIG. 2 ).Notably, the boundaries of the encoded codeword are known at this pointof process 300. In step 308, codeword analyzer 112 may process thescrambled codeword utilizing a receiver FEC decoder element (e.g.,conduct an FEC correction process using the appended checksuminformation). In some embodiments, the FEC decoder element can be aReed-Solomon FEC algorithm. For example, the Reed-Solomon FEC algorithmcan be a RS(514, 544) decoder that is configured to decode codewords orblocks that are passed through.

In some embodiments, the FEC decoder of codeword analyzer 112 counts thenumber of FEC symbols with one or more bit errors. If the number ofsymbols with one or more bit errors is less than or equal to 15, thenthe FEC codeword may be marked as correctable. If the number of FECsymbols with one more bit errors is greater than 15, codeword analyzer112 may indicate that the codeword is uncorrectable.

Notably, this exemplary FEC decoder algorithm is configured to correctup to 15 symbol errors. In the event that the number of symbol errors is15 or less, codeword analyzer 112 and/or FEC decoder is configured toproduce an error corrected codeword that can be processed normally bycodeword analyzer 112 (i.e., advance along the “normal” receiver FECdata path including descrambler step 312 and reverse transcoding step314). Prior to any further processing, codeword analyzer 112 copies anddesignates the last 58 bits of the currently processed codeword as a“bit scrambler seed” in step 310. Notably, the 58 bit scrambler seed isstored should a subsequent codeword be deemed to contain uncorrectabledata (as described in detail below).

Returning to the normal FEC data path processing, codeword analyzer 112is configured to descramble the error corrected data output from the FECdecoder, such that the codeword payload data can be determined (e.g.,step 312). Moreover, the descrambled data can then be forwarded to areverse transcoder element in codeword analyzer 112 that is configuredto de-transcode (e.g., see step 314) the unscrambled codeword, whichproduces the raw original bitstream data (e.g., FEC decoded ingressbits). The raw original bitstream data is then received andappropriately processed by the test device (see step 316).

Notably, the normal receiving FEC receiving data path cannot be executedin the event the codeword is designated as uncorrectable by the codewordanalyzer 112 after processing by the FEC decoder in step 308. Morespecifically, the ideal test scenario involves the device under test (orinterposed link) introducing less than 16 symbol errors in thetransmitted codeword, thereby enabling the FEC decoder of codewordanalyzer (or a separate receiver port) to faithfully regenerate theoriginal bits that were transmitted by codeword generator 108 (or aseparate transmission port) and display the original bits to a testsystem operator. For example, a reconstructed codeword can be useddisplay the location of symbol errors using lanes marked on a relateduncorrectable codeword.

However, if the FEC decoder algorithm determines that there are 16 ormore symbol errors present in the decoded codeword, codeword analyzer112 is triggered to execute a reconstruction process (e.g., codewordreconstruction engine 122 in FIG. 1 ) that is initiated by obtaining a58 bit scrambler seed segment of a previously processed codeword.Specifically, in the event that there are more than 15 symbol errorswithin the one received codeword, the receiving FEC decoder is not ableto determine the true value of the block or codeword. In such cases, thereceiving FEC decoder can only determine that the received block iscorrupted (e.g., uncorrectable) as well as notify a test system user ofthis determination. In some embodiments, the codeword analyzer 112 istriggered to execute a reconstruction process based on any predefinedconditions established by the operator (e.g., predefined threshold ofuncorrectable symbol errors, specific lane position of uncorrectablesymbol errors, specific number of lanes containing uncorrectable symbolerrors, or any other like dynamic criteria established by user). Theaforementioned reconstruction process is described in FIG. 4 in greaterdetail.

FIG. 4 illustrates a flow diagram of the reconstruction process 400executed by codeword reconstruction engine 122 and/or codeword analyzer112. As indicated above, the receiving FEC decoder in codeword analyzer112 may be configured to detect that more than 15 symbol errors arecontained within the received encode codeword. In the event that 16 ormore symbol errors are detected, reconstruction process 400 istriggered. For example, reconstruction process 400 initiates in block402 where a particular transcoded known idle message payload (or someother known transcoded data payload) is received by codewordreconstruction engine 122 as a block of unscrambled data. In someembodiments, the reconstruction engine can construct the idle payload inthe same manner as the transmitter (e.g., steps 202-206 in FIG. 2 ).Notably, this is possible because the receiver knows what payload (i.e.,idle payload) is being transmitted since the transmitter and thereceiver are components of the same test system (e.g., the transmittercan be configured to provide the payload information to the receiver).As used herein, the idle message payload is a group of packets that isrepetitively transmitted during a period where data is unavailable fortransmission. Codeword reconstruction engine 122 further utilizes storedbit seed data 403 associated with the previously processed codeword(which was previously designated as being valid) in step 401 in order toreconstruct a codeword that has been deemed uncorrectable (in process300 in FIG. 3 ).

In step 404, the scrambler algorithm receives the 58 bit seed data whichis used to generate a scrambler seed. In some embodiments, the scrambleseed is the previously processed 58 bits (i.e., at the start of thereconstruction process, the 58 bit seed of the previous correctablecodeword is used) is applied to a polynomial algorithm associated withthe FEC decoder being utilized. For example, the polynomial algorithmoutput of the last 58 bits of the previously valid codeword (aspreviously stored) produces the scrambler seed and the next 5140 bits ofthe transcoder transmit payload can be reconstructed using the idlemessage bits as payload data. This block of 514 data symbols (of 10 bitseach) is then passed through a FEC checksum calculator (see step 406) toderive the associated 30 checksum symbols. Notably, the reconstructedcodeword produced in step 408 is 544 symbols long (i.e., 514 datasymbols+30 checksum symbols). Notably, reconstruction process 400requires at least one previously processed valid/correctable codeword inorder to create the necessary scrambler seed. Reconstruction process 400is described in greater detail below in FIG. 5 .

FIG. 5 is a flow diagram illustrating an exemplary process 500 forreconstructing uncorrectable FEC data. Referring to FIG. 5 , in step502, a bit sequence is generated. In some embodiments, a test deviceincludes a transmission port that is configured to transcode thegenerated bit sequence. For example, codeword generator 108 illustratedin FIG. 1 may generate a pseudo-random bit sequence, segment the bitsequence into a block, and convert the block to an encoded codeword(e.g., transcode, scramble, and derive/append checksum) for transmissionto a component under test (e.g., a SUT, DUT, or link) to be tested.

In block 504, an egress FEC encoded codeword that includes a payloadcontaining the transcoded bit sequence is transmitted over a link orthrough a device under test. For example, a codeword payload containingthe generated bit sequence is initially transmitted to a device undertest, which in turn subsequently forwards the codeword payload to areceiving port of the test device.

In block 506, the FEC encoded codeword transmitted via the DUT (orthrough a link being tested) is received. In some embodiments, areceiver port of the test system receives the encoded codeword as aseries of codewords (or blocks) containing bits of data. For example,the receiver port of the test system may receive a block “N” at time“T”.

In block 508, it is determined that the encoded contents of the FECencoded codeword contains a number of symbol errors that exceeds apredefined threshold. For example, the codeword reconstruction engine inthe codeword analyzer may determine that the codeword contains more than15 symbol errors. Notably, the number of symbol errors exceeds apredefined value thereby rendering the codeword to be designated asuncorrectable. In particular, the true value of the associated codewordcannot be determined. In contrast, if the number of symbol errors doesnot exceed the threshold, the codeword may be identified as correctableand the receiving operation of the codeword analyzer proceeds normally.

In block 510, stored scramble seed bits corresponding to an immediatelypreceding FEC encoded codeword and the transcoded known bit sequence areutilized to generate a reconstructed codeword. At this stage, thecodeword reconstruction engine is further configured to determine thetranscoded value of an idle payload. In some embodiments, storedscrambler seed bits corresponding to an immediately preceding FECencoded codeword (e.g., codeword “N−1” received at time “T−1”) and thetranscoded known bit sequence are utilized to establish a scramble bit.In some embodiments, the codeword reconstruction engine is configured toretrieve the previously stored 58 bit seed (e.g., stored scramble seed)associated with codeword N−1. Utilizing the 58 bit scramble seed and thescrambler polynomial, the codeword reconstruction engine is configuredto generate a (first) scramble bit.

In one example scenario, the codeword reconstruction engine isconfigured to scramble the idle payload using the 58 bit seed (e.g.,stored scramble seed). In particular, the codeword reconstruction engineutilizes the 58 bit seed from codeword N−1 along with the transcodedvalue (e.g., a first transcoded bit) of the idle payload to compute apredicted value for the scrambled block N (i.e., the predicted and/orreconstructed block). The codeword reconstruction engine is furtherconfigured to compute and append checksum information to thereconstructed block N to form a reconstructed codeword N. Notably, thereconstructed codeword can be used to predict the locations of all thebit errors contained within in the uncorrectable codeword. In someembodiments, the reconstructed codeword N (i.e., block N with appendedchecksum information) is presented and or made available to a testsystem user via a graphical user interface.

It will be understood that various details of the subject matterdescribed herein may be changed without departing from the scope of thesubject matter described herein. Furthermore, the foregoing descriptionis for the purpose of illustration only, and not for the purpose oflimitation.

1. A method for reconstructing uncorrectable forward error correction(FEC) data, the method comprising: generating and transcoding a knownbit sequence; transmitting a FEC encoded codeword that includes apayload containing the transcoded known bit sequence through a componentunder test; receiving the FEC encoded codeword transmitted via thecomponent under test; designating the FEC encoded codeword as anuncorrectable codeword in response to determining that encoded contentsof the FEC encoded codeword contains a number of symbol errors thatexceeds a predefined threshold; and utilizing stored scramble seed bitscorresponding to an immediately preceding FEC encoded codeword and thetranscoded known bit sequence to generate a reconstructed codewordassociated with the FEC encoded codeword, wherein the preceding FECencoded codeword is a codeword that was processed before the FEC encodedcodeword.
 2. The method of claim 1 wherein the bit sequence comprises aknown pseudo-random bit sequence.
 3. The method of claim 1 whereintransmitting the bit sequence through a component under test comprisestransmitting the bit sequence over an Ethernet link.
 4. The method ofclaim 1 wherein the stored scramble seed bits and a transcoded data bitare applied to a polynomial associated with a FEC decoder to produce ascrambled bit of the reconstructed codeword.
 5. The method of claim 4wherein the FEC decoder is a Reed-Solomon error correcting code.
 6. Themethod of claim 1 wherein the reconstructed codeword displays thelocation of symbol errors using lanes marked on a related uncorrectablecodeword.
 7. The method of claim 6 wherein the reconstructed codeword isutilized to predict locations of symbol errors in the known bitsequence.
 8. A system for reconstructing uncorrectable forward errorcorrection (FEC) data, the system comprising: a codeword generatorconfigured for generating and transcoding a known bit sequence andtransmitting a FEC encoded codeword that includes a payload containingthe transcoded known bit sequence through a component under test; acodeword analyzer configured for receiving the FEC encoded codewordtransmitted via the component under test and designating the FEC encodedcodeword as an uncorrectable codeword in response to determining thatencoded contents of the FEC encoded codeword contains a number of symbolerrors that exceeds a predefined threshold; and a codewordreconstruction engine for utilizing stored scramble seed bitscorresponding to an immediately preceding FEC encoded codeword and thetranscoded known bit sequence to generate a reconstructed codewordassociated with the FEC encoded codeword, wherein the preceding FECencoded codeword is a codeword that was processed before the FEC encodedcodeword.
 9. The system of claim 8 wherein the bit sequence comprises aknown pseudo-random bit sequence.
 10. The system of claim 8 wherein thecodeword generator is further configured for transmitting the bitsequence over an Ethernet link.
 11. The system of claim 8 wherein thestored scramble seed bits and a transcoded data bit are applied to apolynomial associated with a FEC decoder to produce a scrambled bit ofthe reconstructed codeword.
 12. The system of claim 11 wherein the FECdecoder is a Reed-Solomon error correcting code.
 13. The system of claim8 wherein the reconstructed codeword displays the location of symbolerrors using lanes marked on a related uncorrectable codeword.
 14. Thesystem of claim 13 wherein the reconstructed codeword is utilized topredict locations of symbol errors in the known bit sequence.
 15. Anon-transitory computer readable medium having stored thereon executableinstructions that when executed by a processor of a computer control thecomputer to perform steps comprising: generating and transcoding a knownbit sequence; transmitting a FEC encoded codeword that includes apayload containing the transcoded known bit sequence through a componentunder test; receiving the FEC encoded codeword transmitted via thecomponent under test; designating the FEC encoded codeword as anuncorrectable codeword in response to determining that encoded contentsof the FEC encoded codeword contains a number of symbol errors thatexceeds a predefined threshold; and utilizing stored scramble seed bitscorresponding to an immediately preceding FEC encoded codeword and thetranscoded known bit sequence to generate a reconstructed codewordassociated with the FEC encoded codeword, wherein the preceding FECencoded codeword is a codeword that was processed before the FEC encodedcodeword.
 16. The non-transitory computer readable medium of claim 15wherein the bit sequence comprises a known pseudo-random bit sequence.17. The non-transitory computer readable medium of claim 15 whereintransmitting the bit sequence through a component under test comprisestransmitting the bit sequence over an Ethernet link.
 18. Thenon-transitory computer readable medium of claim 15 the stored scrambleseed bits and a transcoded data bit are applied to a polynomialassociated with a FEC decoder to produce a scrambled bit of thereconstructed codeword.
 19. The non-transitory computer readable mediumof claim 18 wherein the FEC decoder is a Reed-Solomon error correctingcode.
 20. The non-transitory computer readable medium of claim 15wherein the reconstructed codeword displays the location of symbolerrors using lanes marked on a related uncorrectable codeword.